1. Technical Field
The inventive concept relates to a vertical semiconductor device and a method of manufacturing the same, and more particularly, to a vertical semiconductor device with improved junction profile of a buried bit line junction region and a method of manufacturing the same.
2. Related Art
As integration of semiconductor devices increases, channel lengths is of transistors become shorter. The reduction of the channel length leads to a short channel effect such as drain induced barrier lowering (DIBL), a hot carrier effect, and punch through. Methods to solve this problem include a method for reducing a depth of a junction region or a method of relatively increasing a channel length by forming a recess in a channel region of a transistor.
However, as integration of semiconductor memory devices, especially dynamic random access memories (DRAMs), approach Giga bytes, methods to fabricate transistors having smaller size have been required. That is, transistors of Giga byte-graded DRAMs require device dimensions of below 8F2 (F: minimum feature size) and further require device dimensions of about 4F2. Accordingly, although the channel length is scaled down, it is difficult to satisfy the required device dimension in a plan transistor structure in which a stack gate is disposed on a semiconductor substrate and junction regions are disposed at both sides of the stack gate.
Vertical semiconductor devices have been suggested to solve this problem. The conventional vertical semiconductor devices are fabricated by making a bit line region to be open, filling a doped polysilicon layer within a trench between pillars, and forming a buried junction region by performing a heat treatment. However, when the doped polysilicon layer is directly deposited on the bit line contact region, dopants within the polysilicon layer are excessively diffused and have trouble forming a buried type shallow bit line junction region.
Conventional methods to prevent this problem include depositing a Ti/TiN layer on the bit line contact region of the pillar and then depositing is the doped polysilicon layer. However, a SiN layer that is not TiSiX is formed at a portion in which a Ti layer is thinly formed by poor step coverage of a Ti/TiN layer formed in the bit line contact region. The SiN layer serves as a diffusion barrier layer so that a junction profile of the bit line junction region becomes non-uniform.
Especially in the case of a Plasma Enhanced Chemical Vapor Etch (PECVE) Ti layer, side step coverage is poorer than bottom step coverage. If the Ti/TiN layer is deposited and then an etch back process is performed, the side portion of the Ti/TiN layer is reduced more than the bottom portion, resulting in a weak barrier function. The Ti layer may be thickly deposited to prevent a diffusion barrier of the dopants by forming the SiN layer. However, it is preferable that the Ti layer is thinly formed with a minimum of TiSi2 in order to easily remove the doped polysilicon layer, after the bit line junction region is formed.